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Senior RTL Verification Engineer; FPGA​/ASIC)

Job in 1000, Amsterdam, North Holland, Netherlands
Listing for: Fortaegis Technologies
Full Time position
Listed on 2026-08-27
Job specializations:
  • Engineering
    Hardware Engineer, Test Engineer, Electronics Engineer
Salary/Wage Range or Industry Benchmark: 90000 - 120000 EUR Yearly EUR 90000.00 120000.00 YEAR
Job Description & How to Apply Below
Position: Senior RTL Verification Engineer (FPGA/ASIC)
Fortaegis is seeking a Design Verification Engineer in Amsterdam to verify RTL designs for FPGA and ASIC-based products. You will develop verification strategies, maintain environments, and collaborate with design and software teams to ensure correct functionality and performance.
The role emphasizes ownership, problem-solving, and staying current with verification tools and best practices in a fast-growing semiconductor company.

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Position Requirements
10+ Years work experience
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