Principal FPGA Tooling Engineer

Compu Flow is a deep tech company based in Amsterdam building state of the art technologies for custom computing systems. We develop Flow Bench, an in-house low-barrier tool for targeting Field Programmable Gate Array (FPGA) based custom compute accelerators. Flow Bench is not yet another High Level Synthesis (HLS) tool, it strategically abstracts massive throughput hardware structures as streaming dataflow modules, making implementations more efficient, controllable and faster.
We are building our internal Flow Bench hardware development team responsible for the HDL generation and vendor tool integration. As a principle hardware engineer at Compu Flow your role spans the stack from the bottom layer of the FPGA (think constraints, floor planning, and timing&resource analysis) up through development of high-performance HDL templates and (in partnership with the Flow Bench software team) their seamless integration into the already existing, C++ based generator and simulator of streaming accelerators.

You will drive the definition and development of new features, support of additional hardware platforms and analyse generated designs to improve the quality of our generated code and provide the software team with feedback to improve the accuracy of our high-level simulator. As the founding member of the hardware team you will be pivotal in driving decision making and building our system architecture and become the natural leader as the team will be expanded in the future.
Your core responsibilities:  At the top level your job is to design and implement the HDL generation part of Flow Bench and create a successful roadmap. This means thinking beyond the conventional problems of logic design; you'll need to consider broad questions in system architecture, streaming hardware design, clock distribution and modularity to ensure that the HDL templates and hardware generation functionality work across different customer environments.

This will include:
Own the system architecture and development of Flow Bench’s HDL-generation backend;
Design, implement, verify, and maintain templated reusable HDL components generated or instantiated by Flow Bench;
Work effectively in a C++ codebase, in close collaboration with the software team;
Integrate generated designs with FPGA platforms, vendor IP blocks, and vendor or third party tool chains;
Analyze synthesis, timing, area, and resource-utilisation results to improve generated designs and Flow Bench simulator accuracy;
Ensure the readability, maintainability, testability, and predictability of the generated HDL;
Investigate and solve issues across the boundary between compiler-generated hardware output, produced RTL code, simulation, synthesis, and implementation;
Collaborate closely with the teams working on Flow Bench frontend development and customer projects;
Make architectural and strategic decisions to lead the definition of the Flow Bench hardware roadmap;
Over time, help recruit, mentor, and provide technical leadership to additional members of the Compu Flow hardware team.
Who you are   You have strong HDL development skills and at least five years of experience in designing non-trivial logic for FPGAs;
Strong proficiency in at least one HDL, such as VHDL, Verilog, or preferably System Verilog;
Deep practical experience with at least one major FPGA platform and its associated vendor toolchain (preferably Xilinx/AMD);
Having basic experience with software development in C/C++;
An interest in compiler technology, hardware-generation tools, domain-specific architectures, or performance optimization;
You enjoy solving open-ended technical challenges;
You have experience providing technical leadership, mentoring engineers or setting engineering directions;
You work independently and collaborate effectively in international teams;
You communicate clearly in English;
You hold at least a bachelor’s degree in electrical engineering, computer engineering, computer science, or a related field.
What you will get  At Compu Flow, you will work directly with a small, highly experienced team with backgrounds in both academia and industry. Our office in Amsterdam is right next to Sloterdijk train station and we offer hybrid working. You will be able to deliver significant changes and have high autonomy in decision making contributing to an innovative tool for FPGA programming.

We are starting to build out our hardware team with a vision to increase the number of team members over the next few years. You will be the natural lead of this team. Additionally, you will become an important part of the company management team.
We offer a competitive salary based on your experience and contributions and a highly flexible work environment. Given the importance of this role joining the founding team and an equity component is possible based on experience. Wanting to make a difference is essential.

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