Lead Chiplet & Power Architect
Listed on 2026-10-30
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Engineering
Systems Engineer
TYLsemi, Inc. is seeking a Lead Performance Architect to drive architectural configuration, system-level simulation, and PPA optimization for chiplet integration including PCIe, UCIe, and NoC IPs.
You will own trade-off analyses that determine what gets taped out and work with ESL tools to model full-chiplet behavior. Qualifications include 6+ years in computer architecture, hands-on ESL tool experience, and strong Python and SystemC skills.
We invite applications for the Lead Chiplet Performance & Power Architect position located in San Jose, CA, United States.
The position is based in San Jose, CA, United States.
This opportunity is part of our work in Engineering.
The advertised compensation is 204..
This role offers the option to work remotely.
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
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