Senior ASIC STA Engineer — Timing Chip Mastery
Listed on 2026-10-30
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Engineering
Electronics Engineer
Tensordyne, a Sunnyvale-based AI system solutions company, is seeking a senior ASIC STA lead to drive frontend physical design and timing closure across full-chip and block-level work streams. You will collaborate with a global team, develop scalable STA workflows, and optimize timing with Cadence/Synopsys tools in a fast-paced HPC environment.
Ideal candidates have 10+ years in ASIC design, strong SDC skills for PCIe/Ser Des interfaces, and a track record leading backend teams, while enjoying a
Join us at Tensordyne as our next Senior ASIC STA Engineer — Timing & Full-Chip Mastery in Sunnyvale, CA, United States.
As a Senior ASIC STA Engineer — Timing & Full-Chip Mastery, you will play an important part at Tensordyne in Sunnyvale, CA, United States.
We invite applications for the Senior ASIC STA Engineer — Timing & Full-Chip Mastery position located in Sunnyvale, CA, United States.
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