Senior FPGA Architect AI-Driven Hardware

Palo Alto Networks is seeking an experienced FPGA/ASIC design engineer to own architecture, RTL, timing closure, and lab bring-up for high‑performance firewall platforms. You will collaborate with software and hardware teams to deliver silicon for next‑generation devices.

You’ll synthesize using Vivado/Quartus, verify with FPGA prototyping, and optimize resources while integrating IP blocks such as PCIe, Ethernet, and memory controllers. Strong System Verilog & debugging skills are required.

We would love to welcome a new Senior FPGA Architect for AI-Driven Hardware to our organisation in CA, United States.

We are looking to fill the Senior FPGA Architect for AI-Driven Hardware position at Jobs Paloaltonetworks in CA, United States.

The Senior FPGA Architect for AI-Driven Hardware role at Jobs Paloaltonetworks is now open for applications in CA, United States.

Join us at Jobs Paloaltonetworks as our next Senior FPGA Architect for AI-Driven Hardware in CA, United States.