Distinguished Engineer, SerDes Clocking

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $500M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical.

Our team is talent-dense andhigh-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard.

About the Role

We are building a world-class Ser Des engineering organization to enable next-generation, ultra-high-speed connectivity for AI data centers and high-performance computing.

We are seeking an exceptional technical leader to define the clocking architecture for next-generation Ser Des, spanning ultra-low-jitter phase-locked loops (PLLs) and high-performance clock distribution networks.

This is a senior individual contributor role for a recognized expert in high-speed clocking technology who can drive architectural innovation, lead critical circuit development, and solve some of the most challenging jitter, coupling, and power-efficiency problems in advanced CMOS.

You will establish the clocking architecture and design methodology for our next-generation Ser Des platform, working across analog, mixed-signal, digital, layout, and system teams to deliver exceptional timing performance in advanced process technologies at 5nm and below.

Responsibilities:

• Clocking Architecture: Define and drive the end-to-end clocking architecture for next-generation Ser Des, including PLLs, clock generation, multiphase clocking, clock distribution, and integration with transmitter and receiver subsystems.
• Ultra-Low-Jitter PLL Design: Lead the architecture and development of ultra-low-jitter PLLs targeting less than 100 fs RMS integrated jitter in advanced CMOS technologies at 5nm and below, meeting stringent system-level timing and noise requirements.
• PLL Architecture Innovation: Evaluate and develop hybrid, digital, and other advanced PLL architectures, making informed trade-offs among jitter, power, area, tuning range, robustness, and implementation complexity.
• Multi-PLL Coupling Management: Develop architectural and circuit-level solutions to mitigate coupling among multiple PLLs and clock-generation blocks, including supply coupling, substrate noise, electromagnetic interactions, reference spurs, and clock-to-clock interference.
• Power-Efficient Clock Distribution: Define and implement advanced clock distribution architectures, including resonant clocking techniques, to reduce clocking power while maintaining stringent jitter, skew, phase-noise, and timing requirements.
• EM Analysis and Optimization: Use electromagnetic simulation and extraction tools to analyze and optimize inductors, resonant networks, clock distribution structures, coupling paths, and high-frequency interconnects.
• Modeling and Verification: Develop System Verilog-based behavioral models, verification environments, and architectural models for PLLs and clocking subsystems to enable early system integration, design exploration, and verification of key performance requirements.
• Cross-Functional Technical Leadership: Partner with Ser Des TX, RX, ADC, digital, AMS layout, package, and silicon validation teams to optimize overall link performance and ensure clocking architecture decisions align with system requirements.
• Silicon Execution and…