Senior Photonic Layout Engineer - Tape- Lead
Listed on 2026-11-05
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Engineering
Electronics Engineer
Acceler8 Talent seeks a Senior Photonic Layout Engineer in Berkeley, CA, to own the photonic layout and tape-out flow, interfacing PIC development with electronic IC work. The role emphasizes Cadence-based workflows for a 45 nm process and close collaboration across PIC, EIC, and packaging teams.
Candidates should have direct PIC design ownership, strong Cadence experience, and a track record of tape-out-ready photonic designs, including foundry PDKs and DRC/LVS alignment.
We are looking to fill the Senior Photonic Layout Engineer
- Tape-Out Lead position at Acceler8 Talent in CA, United States.
We would love to welcome a new Senior Photonic Layout Engineer
- Tape-Out Lead to our group in CA, United States.
For the Senior Photonic Layout Engineer
- Tape-Out Lead position at Acceler8 Talent, we are reviewing applications now.
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