FPGA Verification Engineer Security Clearance

Position: FPGA Verification Engineer with Security Clearance
Key Responsibilities:

• Creating automated test frameworks
• Applying formal methods for security-critical design blocks

• Expert knowledge of System Verilog and UVM

• Knowledge of Register-transfer level (RTL)
• Demonstrated experience with formal verification tools and assertion-based verification

• Collaborating with RTL developers to ensure design quality Desired Skills:
• Experience with Cadence Jasper Gold or similar formal tools,
• Knowledge of security protocols and formal security proofs,
• System Verilog Assertions (SVA)
• Background in mathematical logic and proof systems. Required Education,

Experience and Skills:

• Bachelor's degree in Electrical / Computer Engineering,
• 7+ years of FPGA verification experience