Principal or Senior Analog Design Engineer

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You are a seasoned analog design engineer with deep expertise in high-speed SERDES IP. You thrive on solving complex circuit challenges, leading technical initiatives, and collaborating across multidisciplinary teams. Your track record in advanced CMOS design, effective communication skills, and passion for innovation make you a trusted mentor and a key contributor to project and team success.

• Develop and specify SERDES transceiver architectures and sub-blocks based on standards.
• Design, simulate, and verify high-speed analog circuits for optimal power and performance.
• Collaborate with analog, digital, and CAD teams to ensure design quality and efficiency.
• Present technical results internally and externally to customers and industry groups.
• Oversee physical layout to address parasitics and reliability concerns.
• Document features and test plans, and support post-silicon analysis and updates.

• Advance industry-leading SERDES IP for next-generation SoCs.
• Enhance product differentiation and customer value.
• Streamline design processes for quality and time-to-market.
• Mentor junior team members and share best practices.
• Influence technical direction and innovation at Synopsys.
• Support customer success and product reliability.

• Ph.D. with 6+ years or M.Sc. with 8+ years of analog IC design experience.
• Expertise in transistor-level CMOS design and SERDES sub-circuits.
• Proficiency with schematic, layout, and verification tools; SPICE simulators.
• Experience with scripting languages (Verilog-A, TCL, Python, etc.).
• Strong communication and documentation skills.

• Technical leader and mentor
• Collaborative and proactive
• Analytical and detail-oriented
• Adaptable and innovative

A collaborative, high-performing analog and mixed-signal design group focused on developing advanced SERDES IP for leading-edge applications. The core purpose of the team is the development of 224‑Gb/s Ethernet Ser Des Transceivers for network infrastructure ICs, driving the future of high-speed connectivity in data centers and communications networks for the world.