Senior ASIC Physical Design Engineer, Cache Coherent Interconnects

Senior ASIC Physical Design Engineer, Cache Coherent Interconnects page is loaded## Senior ASIC Physical Design Engineer, Cache Coherent Interconnects locations:
US, CA, Santa Clara:
US, TX, Austin:
US, TX, Remote:
US, OR, Hillsboro:
US, CA, Remote time type:
Full time posted on:
Posted Yesterday job requisition :
JR2008539

As a member of our CPU Cache Coherent Interconnects Design Team, you will be responsible for the physical design of CPU on-chip interconnect network and last-level caches, working on implementation, synthesis and timing closure while collaborating closely with the logic design team on micro-architecture definition and feasibility. This position offers you the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

We have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.
** What you'll be doing:
*** As a member of our CPU team, you'll be a liaison between Logic design and Physical design teams responsible for achieving timing, area, performance and power goals of the unit.
* Help define the architecture for next-generation Nvidia coherent interconnects and system-level caches.
** What we need to see:
*** Master’s Degree in Electrical Engineering, Computer Engineering or Computer Science or equivalent experience.
* 5+ years of experience in processor or other related high-performance semiconductor designs.
* Physical design expertise including hands-on synthesis experience, timing analysis, floor-planning and in-depth knowledge of industry standard physical design tools is required.
* Physical design expertise in high-frequency interconnect/cache/core design is preferred.
* Verilog expertise is preferred as is a deep understanding of ASIC design flow including RTL design and verification, DFT, and ECO.
* Strong communication and interpersonal skills are required along with the ability to work in a dynamic, global team. #LI-Hybrid Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 212,750 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.You

will also be eligible for equity and .Applications for this job will be accepted at least until November 23, 2025.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
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