CPU RTL Design Engineer; level - Cambridge, UK

Company

Qualcomm Technologies International Ltd

Engineering Group, Engineering Group > ASICS Engineering

Cambridge is Qualcomm's largest office in the UK, with about 400 team members including engineers, business strategists and support staff. From an engineering perspective, we have teams focussing on: RF and PMU analog design, digital design & verification, digital physical design, embedded software, packaging and post-silicon validation. Target products include: high performance CPUs and GPUs, ultra‑low power IoT devices, and wearables such as smart glasses, smart watches and earbuds.

We are hiring talented engineers for CPU RTL development targeted for high performance, low power devices. As a CPU Micro‑architecture and RTL Design Engineer, you will work with chip architects to conceive of the micro‑architecture, and also help with architecture/product definition through early involvement in the product life‑cycle.

* Please note this role will require 5 days per week onsite in our Cambridge office*

• Performance exploration. Explore high performance strategies working with the CPU modelling team.
• Microarchitecture development and specification. From early high‑level architectural exploration, through micro architectural research and arriving at a detailed specification.
• RTL ownership. Development, assessment and refinement of RTL design to target power, performance, area and timing goals.
• Functional verification support. Help the design verification team execute on the functional verification strategy.
• Performance verification support. Help verify that the RTL design meets the performance goals.
• Design delivery. Work with multi‑functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and power.

• Thorough knowledge of microprocessor architecture including expertise in one or more of the following areas: instruction fetch and decode, branch prediction, instruction scheduling and register renaming, out‑of‑order execution, integer and floating point execution, load/store execution, prefetching, cache and memory subsystems.
• Knowledge of Verilog and/or VHDL. Experience with simulators and waveform debugging tools.
• Knowledge of logic design principles along with timing and power implications.
• Understanding of low power microarchitecture techniques.
• Understanding of high performance techniques and trade‑offs in a CPU microarchitecture.
• Experience using a scripting language such as Perl or Python.

Apart from working in an open, relaxed and collaborative space, you will enjoy:

• Salary, stock and performance related bonus
• Maternity/Paternity Leave
• Employee stock purchase scheme
• Matching pension scheme
• Education Assistance
• Relocation and immigration support
• Life, Medical, Income and Travel Insurance
• Subsidised gym membership
• Bicycle purchase scheme

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
• Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

* References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e‑mail disability‑ or call Qualcomm's toll‑free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process.

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