Mixed Signal Design Engineer

We are a well‑funded semiconductor technology company developing next‑generation programmable coherent DSP solutions for cloud and AI infrastructure. Our technology enables faster and more efficient data transmission within and between AI data centers, forming a critical foundation for the future of high‑speed connectivity and AI‑driven systems.

Seeking an experienced Mixed Signal Verification Engineer to support the development and verification of advanced high‑speed communication systems. The ideal candidate will have strong expertise in behavioral modeling, mixed‑signal verification, and UVM‑based methodologies, along with excellent collaboration and communication skills.

Fully onsite role in Austin, TX (5 days per week).

• Develop verification strategies for digital and analog (mixed‑signal) designs using UVM methodologies based on design specifications
• Create behavioral models (BM) for analog blocks following guidelines from analog design teams
• Write, execute, debug, and maintain UVM‑based test benches using System Verilog for mixed‑signal designs
• Run and debug behavioral model validation using AMS tools to ensure correctness and coverage
• Perform and troubleshoot unit‑level, cluster‑level, and top‑level simulations of mixed‑signal designs
• Collaborate closely with analog and digital design teams to ensure verification completeness

• Current and recent experience as a Mixed Signal / Signal Verification Engineer
• Minimum 5 years of experience in behavioral modeling (BM) of analog designs for digital verification
• Strong knowledge of mixed‑signal dynamic verification using chip digital design tools (no AMS dependency)
• Hands‑on experience with Verilog / System Verilog
• Solid understanding of verification methodologies and tools, including UVM, Specman, AMS, simulators, waveform viewers, execution automation, and coverage collection
• Basic understanding of analog design concepts
• Job stability required (no frequent job changes)
• No employment gaps will be considered

• Experience with Virtuoso Schematics
• Experience using both Synopsys and Cadence tool chains
• Proven ability to develop scalable and portable verification environments and test cases
• Ability to work effectively in a collaborative, cross‑functional mixed‑signal verification team
• Strong communication skills, including documentation, test planning, and presentation of results

• Onsite role in Austin, TX (5 days/week mandatory)
• Long‑term opportunity within a fast‑growing semiconductor technology organization
• Visa sponsorship (H‑1B) may be available

• Seniority level:
  Mid‑Senior level
• Employment type:
  
  Full‑time
• Job function:
  Manufacturing
• Industries:
  Semiconductor Manufacturing