DFT Design Engineer

DFT Design Engineer

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Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let’s do something wonderful together. Join us, because at Intel, we are building a better tomorrow.

Job Description:

Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth.

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• Life at Intel
• Intel Global Diversity and Inclusion

• Develop logic design, register transfer level (RTL) coding, simulation, and provide DFT timing closure support as well as test content generation and delivery to manufacturing for various DFx content (including SCAN, MBIST, and BSCAN).
• Participate and collaborate in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed (including TAP, SCAN, MBIST, BSCAN, proc monitors, in system test/BIST).
• Develop HVM content for rapid bring up and ramp to production on the automatic test equipment (ATE).
• Apply various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT.
• Optimize logic to qualify the design to meet power, performance, area, timing, test coverage, DPM, and test time/vector memory reduction goals as well as design integrity for physical implementation.
• Review the verification plan and drive verification of the DFT design to achieve desired architecture and microarchitecture specifications.
• Ensure design features are verified correctly and resolve and implement corrective measures for failing RTL tests to ensure correctness of features.
• Integrate DFT blocks into functional IP and SoC and support SoC customers to ensure high-quality integration of the IP block.
• Collaborate with post silicon and manufacturing team to verify the feature on silicon, support debug requirements, and document all learnings and improvements requirement in design and validation.
• Drive high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product and develop HVM content for rapid bring up and production on the ATE.

Minimum Qualifications

Bachelor’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field with 3+ years of relevant experience; or Master’s degree in the same fields with 2+ years of relevant experience; or PhD in the same fields with 1+ year of relevant experience.

Relevant Work Experience Should Be Of The Following

• Experience with DFT Array Test including MBIST or Scan/ATPG or DFT Verification.

Preferred Qualifications

• Expertise in Tessent DFT tool.
• Expertise in Primetime especially in DFT constraints.
• Expertise in Quality checks such as Lint, VCLP, CDC/RDC, LEC, Spyglass DFT.

Experienced Hire

Shift 1 (United States of America)

US, California, Santa Clara

US, Oregon, Hillsboro; US, Texas, Austin

At the Data Center Group (DCG), we’re committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership.

Join us as we transform the data center segment through workload-driven leadership products and close collaboration with our partners.

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information,…