Senior Design Verification Engineer: SoC RTL​/UVM Specialist

A leading technology company is seeking a Senior Design Verification Engineer in Austin, Texas. The ideal candidate will have over 10 years of experience in semiconductor ASIC and a strong proficiency in System Verilog and UVM. Responsibilities include architecting verification environments and developing test plans for complex functional blocks. Join an innovative team committed to enhancing hardware designs and delivering exceptional results.
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