Senior Physical Design Methodology Engineer, Innovus Flows

Do you have a passion for computer gaming, virtual reality, computer vision, and artificial intelligence? Ever dream about inventing your own holodeck? Do you want to work on groundbreaking problems alongside some of the most forward-thinking people in the world?

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities which are hard to solve, that only we can pursue, and that matter to the world.

This is our life’s work, to amplify human inventiveness and intelligence.

• Developing innovative physical design methodologies for implementation of GPU, CPU and SOCs, with emphasis on PPA (Power, Performance, Area) and runtime improvement of the physical design flow on advanced technology nodes
• Develop flows for advanced place and route methods, floor planning and chip assembly, power and clock distribution, power and area optimization, timing, IR and EM analysis and closure
• Work with internal and external partners to drive tool and methodology improvements to deliver best-in-class PPA solutions across all our product lines

• MS in Electrical or Computer Engineering (or equivalent experience)
• Minimum 7 years’ experience in Physical Design Engineering
• Proven track record of PPA improvement on high performance and low power designs in advanced technology nodes
• Strong understanding of physical design optimization and routing methodologies at place, cts, route and postroute, especially power and area efficient setup and hold optimization
• Solid background in advanced Clock tree synthesis methods and techniques
• Strong background in STA, extraction, timing and RC correlation
• Good understanding of design rules in advanced nodes and their impact on DRC closure and PPA optimization
• Understanding of power intent files such as UPF, and use of FSDB/SAIFs for power optimization??