Principal Hardware System Design Engineer

Principal Hardware System Design Engineer

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Arm technology is becoming the platform of choice for compute and AI. The Arm System Engineering team’s mission is to architect, design, and develop server and rack-level infrastructure for at-scale datacenter deployments. The team capabilities span across system hardware, software, system interconnect, system management storage, data center infrastructure and performance engineering. The team responsibilities include customer engagements, technology selection, system design, network architecture, performance, and datacenter deployment & operations.

The Arm System Engineering team is developing industry-leading technology to deliver innovative and high‑performing solutions to power the data centers of the future.

The Principal Hardware Design Engineer will play a pivotal role in designing innovative hardware systems for AI/ML applications. This position calls for expertise in electrical engineering principles, a deep understanding of system‑level design, and a strong ability to manage complex projects. Successful candidates will craft innovative solutions that drive performance, reliability, and scalability in AI/ML platforms.

This role will be based in Austin, Texas.

• Responsible for leading the development and implementation of multiple simultaneous system‑level PCBAs.
• Proficient in System Design Implementation, encompassing electrical design, PCB layout, and understanding design constraints across Electrical, Mechanical, Power, Thermal, and Firmware aspects.
• Working with Architecture and other EE Designers on the team, design and implement system‑level management bus topologies spanning multiple boards and devices.
• Oversee the definition of connector pinouts for various high‑speed and low‑speed interconnects.
• Actively participate in prototype builds in the factory followed by deeper in‑lab PCBA checkouts.
• Spearhead the creation and ultimately approve vital board characterization and validation plans to ensure design robustness and full functionality.
• Actively debug and solve hardware issues in the laboratory when required, leading debug efforts across the engineering team, ODM, and customers.
• Collaborate with manufacturing operations to ensure fixtures and test programs provide acceptable test coverage.
• International travel as needed during the program.

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• More than 10 years of experience in server hardware design and server PCBA development.
• Experience in designing complex rack‑level hardware systems involving compute, storage, networking, high‑speed point‑to‑point cabling bus, and power sub‑systems.
• Demonstrated expertise as the responsible engineer on multiple simultaneous PCB/A or system projects.
• Proven experience collaborating in a joint development model with Server ODMs.
• Working knowledge of PCIe, I2C, I3C, MCTP, USB, eSPI, and other common protocols within AI/ML systems.
• Hands‑on experience using oscilloscopes, logic analyzers, and other standard debug tools.
• Strong communication and collaboration skills.
• Ability to perform effectively in a fast‑paced, dynamic environment.

• Have designed and deployed modern AI/ML rack scale systems.
• Experience designing and implementing Arm‑based compute server platforms.
• Familiarity with emerging technologies in AI and Data Center infrastructure.

$241,100-$326,100 per year

At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email  To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation.

Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please…