ASIC Engineer, Implementation – Timing

Meta's Infrastructure Silicon team is looking for an ASIC Implementation Engineer with a specialization in timing to design and deliver custom silicon for data center applications. This role involves driving static timing analysis and ensuring timing closure for complex System on Chip (SoC) designs, focusing on performance, power, and area targets at advanced process nodes.

Responsibilities:

• Develop and maintain timing constraints (SDC) for complex SoC designs, including clock definitions and input/output delays.
• Perform static timing analysis using industry-standard tools to identify and resolve timing violations.
• Collaborate with physical design engineers to drive timing closure, providing guidance on placement and routing.
• Analyze and debug timing paths across multiple clock domains, identifying critical paths and recommending optimizations.
• Generate and validate timing reports for sign-off across various process, voltage, and temperature corners.
• Develop and maintain timing exception methodologies in coordination with design and verification teams.
• Contribute to the development of timing closure scripts and automation flows to enhance efficiency.
• Interface with foundry and library teams to integrate timing libraries, including standard cells and hard IP.
• Support design handoff between front-end and back-end teams by providing timing-aware synthesis netlists.

Qualifications:

• Currently pursuing or holding a Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field.
• 2 years of experience in ASIC implementation focusing on static timing analysis and timing closure.
• Experience with static timing analysis tools such as Prime Time or equivalent.
• Experience developing and validating SDC timing constraints for complex SoC or IP designs.
• Experience with logic synthesis tools and timing-driven optimization techniques.
• Proficiency in scripting languages like Python, Tcl, or Perl for automating timing analysis.

Skills:

• Strong understanding of static timing analysis and timing closure processes.
• Proficient in developing timing constraints and performing timing analysis.
• Ability to collaborate effectively with cross-functional teams.
• Experience with RTL design or synthesis using System Verilog or similar languages is a plus.
• Familiarity with physical design concepts related to timing closure.
• Knowledge of clock tree synthesis and optimization techniques.