Physical Design Engineer- Staff to Sr

Qualcomm Technologies, Inc.

Engineering Group, Engineering Group > ASICS Engineering

QCT’s NSP Physical Design Team is actively seeking a highly experienced Clock Physical Design Engineer to develop, optimize, and sign off advanced clocking solutions for next-generation NSP designs. The ideal candidate will have 10+ years of ASIC/SoC physical design experience, with deep expertise in high-performance clock architecture and implementation, including clock H-trees, clock mesh, and clock spine methodologies.

This role requires strong understanding of the complete clock path, from clock source and distribution architecture through block-level implementation and signoff. The engineer will work across physical design, timing, power, PLL, and CAD teams to optimize clock performance, power, variation, noise, and robustness across advanced technology nodes.

• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
• OR
• Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
• OR
• PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

• Own and drive clock physical design methodology, implementation, optimization, and signoff for complex NSP designs.
• Architect, implement, and optimize advanced clock distribution structures, including:
  • Clock H-trees, Clock mesh architectures, Clock spine methodologies, Hierarchical clock distribution across block and top-level designs, Clock gating and low-power clock distribution techniques
• Perform detailed SPICE simulation and transistor-level analysis of critical clock structures to understand clock waveform quality, delay, slew, sensitivity, and robustness across operating conditions.
• Analyze and debug clock-related:
  • Timing and clock skew, Dynamic and leakage power, Signal integrity and noise, On-chip variation, Jitter and clock uncertainty, Duty-cycle distortion, Slew and waveform degradation, Physical implementation and routing issues
• Drive clock convergence and signoff across multiple modes, process corners, voltage conditions, temperatures, and operating frequencies.
• Analyze clock distribution tradeoffs across performance, power, area, skew, insertion delay, variation, and robustness, and recommend appropriate clock architectures and implementation strategies.
• Provide technical feedback and guidance to block-level and top-level Physical Design engineers on:
  • Required clocking fixes, Clock tree/mesh/spine optimization opportunities, Clock routing and physical implementation issues, Timing and variation concerns, Power reduction opportunities, Potential signoff risks
• Collaborate closely with PLL, STA/timing, power, CAD, RTL, architecture, and implementation teams to align:
  • Clock source assumptions, PLL and clock-source characteristics, Jitter budgets, Clock uncertainty, Clock latency and skew targets, Variation assumptions, MMMC constraints, Clock signoff methodology
• Perform detailed clock timing analysis using Synopsys Prime Time and correlate implementation, STA, extraction, and SPICE results where required.
• Work with implementation teams to develop and tune customized clock implementation recipes and methodologies for aggressive performance and power targets.
• Support clock-related ECO development and implementation during timing closure and tapeout convergence.
• Evaluate clock networks for IR-drop, EM, crosstalk, signal integrity, and reliability risks, and work with implementation and power-integrity teams to resolve issues…