Modeling Engineer Processor, AI Accelerator, and SoC Architecture- Sr

Qualcomm Technologies, Inc.

Engineering Group, Engineering Group > DSP Architecture and Design

We are seeking an experienced Performance Modeling Engineer to drive architectural exploration, performance analysis, and system-level optimization for next-generation processors, AI accelerators, and SoC platforms. The ideal candidate will have deep expertise in processor architecture, memory systems, cache hierarchies, coherent interconnects, and transaction-level modeling (TLM).

In this role, you will work closely with architecture, RTL, verification, software, and system teams to develop high-fidelity performance models, evaluate architectural tradeoffs, and guide key design decisions from concept through silicon.

• Bachelor's degree in Electrical Engineering, Computer Science, Computer Engineering, or related field and 6+ years of Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
• OR
• Master's degree in Electrical Engineering, Computer Science, Computer Engineering, or related field and 5+ years of Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
• OR
• PhD in Electrical Engineering, Computer Science, Computer Engineering, or related field and 4+ years of Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.

• Develop and maintain transaction-level and analytical performance models for processors, memory hierarchies, interconnects, and accelerators.
• Create detailed models of:
  • Cache hierarchies
  • Coherent interconnects
  • Memory subsystems
  • DMA engines
  • Shared-memory multiprocessor (SMP) systems
• Evaluate architectural tradeoffs involving:
  • Performance
  • Power
  • Area
  • Latency
  • Bandwidth
  • Scalability
• Analyze workload behavior and identify system bottlenecks through simulation and modeling.
• Drive architectural studies for next-generation multicore and cache-coherent systems.
• Perform deep performance analysis of:
  • Branch prediction
  • Hardware prefetching
  • Speculative execution
  • Load/store architectures
  • Cache coherence protocols
  • Memory consistency models
• Model and validate the behavior of multithreaded and multiprocessor workloads.
• Collaborate with hardware and software teams to correlate performance models with RTL simulations, emulation results, and silicon data.
• Present architectural recommendations and performance insights to engineering leadership.

• BS, MS, or PhD in Computer Engineering, Electrical Engineering, Computer Science, or related field.
• 10+ years of industry experience in computer architecture, microarchitecture, or performance modeling.
• Strong understanding of:
  • Processor architecture and microarchitecture
  • Cache and memory hierarchy design
  • Shared-memory multiprocessor (SMP) systems
  • Multicore scaling challenges
• Experience developing:
  • Transaction-Level Models (TLM/SystemC)
  • Analytical performance models
  • Architectural simulators
• Deep knowledge of cache behavior, including:
  • Capacity and conflict effects
  • Latency analysis
  • Prefetching techniques
  • Memory locality
  • Coherence interactions
• Familiarity with modern cache coherence protocols such as:
  • ARM CHI
  • ACE
  • MESI/MOESI-based protocols
• Strong understanding of:
  • Memory consistency models
  • Atomic operations
  • Synchronization mechanisms
  • Ordering semantics
• Strong software development skills in C++, Python, or equivalent languages.

• Experience modeling AI accelerators, CPUs, GPUs, or heterogeneous compute architectures.
• Understanding of:
  • Network-on-Chip (NoC) architectures
  • Memory controllers
  • DDR and HBM memory systems
  • Virtualization technologies such as SR-IOV
• Familiarity with formal verification methods for cache coherence and memory ordering.
• Experience correlating pre-silicon performance models…