Sr. Formal Verification Engineer, Leo

Position: Sr. Formal Verification Engineer, Amazon Leo
Amazon's Leo Silicon Team is building next-generation modem SoCs for broadbandcommunication, a constellation of low Earth orbit satellites designed to deliver fast, affordable broadband to unserved and underserved communities around the world. Our Design Verification team is seeking a highly skilled and motivated Senior Formal Verification Engineer to drive formal verification efforts across our complex modem SoC  this role, you will apply rigorous mathematical methods to prove design correctness anduncover corner-case bugs that escape simulation-based verification.

You will serve as a subject matter expert in formal verification methodologies, mentor engineers across the team, and collaborate closely with RTL designers, simulation-based DV engineers, emulation engineers, and architects to shift verification left and improve overall silicon quality. This is a high-impact role on a team that is scaling verification capabilities with each successive tape-out and actively integrating AI-centric verification methodologies.

Export Control Requirement:

Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.

Key job responsibilities Develop and execute formal verification strategies using Jasper Gold and/or Questa Formal for property checking (FPV), connectivity checking (CC), register verification,and sequential equivalence checking (SEQ) Write, review, and debug System Verilog Assertions (SVA) — including assumptions,assertions, and cover properties — to verify complex modem SoC design behaviorsacross NOC, interconnect, modem IPs and control logic Drive convergence on formal proofs by applying abstraction techniques, complexity reduction strategies, and assume-guarantee reasoning Collaborate with RTL designers, architects, and simulation-based DV engineers todefine verification plans that incorporate formal methods alongside UVM-basedsimulation and emulation approaches Champion a "formal-first" verification strategy by identifying and pursuing opportunities to apply formal verification to new design blocks — building on our established formal verification checklist deployed across SoC and NoC partitions Develop reusable formal verification infrastructure, including constraint libraries,parameterized property templates, and automated regression flows integrated into ourCI/CD verification pipeline Contribute to coverage closure strategies by leveraging formal coverage analysis to complement simulation-driven functional coverage Mentor and guide DV engineers in formal verification techniques, SVA best practices,and proof convergence strategies Partner with EDA vendors to evaluate new formal verification capabilities and drivetool improvements that benefit the team Basic qualifications
- Bachelor's degree in electrical engineering, computer engineering, or equivalent- 8+ years of experience in ASIC/SoC design verification with a strong focus on formal verification

- Experience with Jasper Gold and/or Questa Formal
- Strong proficiency in System Verilog Assertions (SVA) and formal property specification

- Experience with formal verification applications: FPV, connectivity checking, register verification, equivalence checking, and coverage analysis
- Demonstrated ability to drive proof convergence on complex designs using abstraction, case-splitting, and assume-guarantee techniques
- Proficiency in System Verilog and UVM concepts
- Proficiency in leveraging AI/LLM tools to accelerate formal verification workflows including AI-assisted SVA generation, property debugging, proof exploration, and automated constraint refinement

Preferred…