Senior Design Verification Engineer

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets.

Learn more at  Design Verification Engineer Austin, Texas Meet the team

The Wireless PHYMAC team is responsible for designing the digital components of Silicon Labs’ low power energy-efficient wireless products. Our team focuses on building efficient, high-performance digital systems that enable wireless connectivity across applications such as smart home, industrial IoT, and smart cities. The team operates in a highly collaborative and cross-functional environment, working closely with system architects, analog/RF designers, firmware engineers, and product teams to deliver robust and scalable wireless solutions.

By working at the intersection of digital design and wireless systems, the team plays a critical role in advancing the future of connected devices.

About the Role As a Senior Design Verification Engineer, you will be responsible for ensuring the functional correctness and performance of digital modem designs used in Silicon Labs’ low-power wireless products. You will work closely with design, architecture, and system teams to develop verification strategies, build robust test environments, and debug complex issues across the PHY/MAC layers.

This role offers the opportunity to contribute throughout the product lifecycle—from early design through silicon bring-up—while working on cutting-edge wireless technologies that power next-generation connected devices.

Responsibilities Define and execute verification strategies for digital modem designs across key wireless use cases

Develop and maintain scalable verification environments using System Verilog/UVM or similar methodologies

Create test plans, test benches, and stimuli to achieve high functional and coverage closure

Debug and analyze design issues, working closely with design and architecture teams to resolve them Track and drive functional and code coverage to ensure verification completeness

Collaborate cross-functionally with firmware, validation, and system teams to ensure correct system behavior

Support silicon bring-up and correlate pre-silicon verification with post-silicon results

Continuously improve verification methodologies, tools, and automation workflows

Minimum Qualifications BSEE/CE or a related field

Solid understanding of digital design fundamentals and verification concepts3-6 years of experience in digital design verification, with a focus on modem or wireless PHY designs preferred

Experience with System Verilog and UVM or similar verification methodologies

Strong debugging skills with experience analyzing simulation results and identifying root causes

Familiarity with scripting languages such as Python or Perl for automation

Basic understanding of wireless communication systems or digital signal processing concepts

Strong problem-solving skills and ability to work effectively in a collaborative team environment

Preferred Qualifications Experience verifying wireless standards such as BLE, Wi-Fi, Zigbee, or similar technologies

Experience with advanced verification techniques such as constrained-random, coverage-driven verification, and System Verilog assertions (SVA)
Familiarity with C/C++ or MATLAB for algorithm modeling and reference model development

Experience…