DPU Performance Architect: Modeling & RTL Validation
Listed on 2026-10-13
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Engineering
Systems Engineer, Hardware Engineer, Test Engineer
Meta's Infrastructure Silicon organization designs custom silicon that powers data center infrastructure—SmartNICs/IPUs/DPUs, AI accelerators, and networking ASICs. We seek an experienced Performance Architect to drive performance modeling, analysis, and validation of DPU architectures, influencing architecture decisions from early path-finding through RTL validation and silicon correlation.
The role demands deep experience in end-to-end performance analysis, workload characterization, and
The DPU Performance Architect:
Modeling & RTL Validation position in the IT & Technology, Engineering field is open for applications.
This opportunity is part of our work in IT & Technology, Engineering.
The advertised compensation is 140..
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
Learn more about the DPU Performance Architect:
Modeling & RTL Validation role in the description above.
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