Static Timing Analysis Design Engineer​/Physical Design

• End-to-End Constraints and Timing Signoff Ownership Drive Timing Constraints Creation and Validation Work with Frontend, IP and DFT teams to Validate Constraints, Resolve timing issues Work hand-in-hand with Implementation owner(s) and Full Chip STA team to close Timing Timing Correlation and Timing Path Debug from synthesis through timing signoff Provide timing feedback during all design stages Create Automated and Manual timing fixes for implementation
• Team Leadership & Organization Development Participate career development. Interface with Implementation owner(s) and Full Chip STA team.
• Technical Strategy & Innovation Provide feedback to improve scalability, productivity, and design quality through methodology enhancements to leadership
• Cross-Functional & Ecosystem Engagement Collaborate with Frontend, IP and DFT teams for Constraint Validation and Timing Issues Support post-silicon bring-up, yield improvement, and production ramp activities.

• STA and signoff methodologies
• Timing ECO Generation (automated and manual)
• Constraints Development and Validation
• Advanced node implementation (≤ 16nm / 5nm)
• Scripting in Python, TCL, and Perl
• Familiarity with using AI to generate scripts

• Bachelor’s or Master’s in Electrical / Electronics Engineering or related field 3-6 years of experience in ASIC / SoC Timing Analysis Strong knowledge of industry STA tools (Synopsys flows) Strong communication skills

• Experience in high-reliability SoCs Exposure to AI-driven design methodologies and automation

Timing closure of flagship SoCs at advanced nodes Direct impact on silicon success and product competitiveness

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