Semiconductor Engineering Director
Listed on 2026-10-16
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Engineering
Systems Engineer, Electronics Engineer, Electrical Engineering
We are conducting a confidential search for a Semiconductor Engineering Director to lead the semiconductor design and process engineering organization within a leading technology company. This is a high-impact, director-level opportunity based in Austin on a hybrid model for a senior engineering leader who will drive chip architecture strategy, oversee ASIC/FPGA development, manage fab partnerships, and advance next-generation node development.
In this role, you will define and execute the semiconductor engineering roadmap, from architecture through tape-out and production. You will lead ASIC and FPGA design teams across RTL design, verification, physical design, and post-silicon validation. You will oversee process engineering and manage relationships with foundry partners (TSMC, Samsung, Global Foundries), and drive adoption of advanced nodes (5nm, 3nm, GAA) and emerging packaging technologies (chiplet, 2.5D/3D).
You will collaborate with systems architecture, firmware, and software teams to optimize SoC performance and power efficiency, manage EDA tool strategy and design methodology improvements, ensure DFM/DFT compliance and yield optimization across all product lines, and build, mentor, and scale a world-class semiconductor engineering team. This is a rare opportunity to shape the engineering trajectory of a cutting-edge semiconductor organization.
Nice to Have- Experience in automotive, AI/ML, or high-performance computing semiconductor applications
- Knowledge of RISC-V architecture and open-source hardware ecosystems
- Experience with advanced packaging technologies (chiplet, 2.5D/3D integration)
- Track record of successful tape-outs at advanced nodes (7nm and below)
- Patent portfolio in semiconductor design or process innovation
- Experience with automotive, AI/HPC, or data center semiconductor applications
- Familiarity with RISC-V architecture
- Experience with advanced packaging (chiplet, 2.5D/3D)
- Track record of successful tape-outs at 7nm or below
- Semiconductor-related patents or publications
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