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CryoCMOS Digital IC Design Engineer, Quantum

Job in Austin, Travis County, Texas, 78716, USA
Listing for: GlobalFoundries
Full Time position
Listed on 2026-10-16
Job specializations:
  • Engineering
    Electronics Engineer, Systems Engineer, Hardware Engineer, Test Engineer
Salary/Wage Range or Industry Benchmark: 98000 - 202000 USD Yearly USD 98000.00 202000.00 YEAR
Job Description & How to Apply Below
About Global Foundries

Global Foundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, Global Foundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit

About Global Foundries

Global Foundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, Global Foundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit

Summary Of Role

Global Foundries is seeking a Senior Digital IC Design Engineer to develop advanced digital and mixed-signal integrated circuits and reusable IP for emerging semiconductor applications, including cryogenic CMOS and quantum systems. This role will drive designs from architecture and RTL through physical implementation, tapeout, and silicon validation while partnering closely with technology, PDK, modeling, verification, and test teams.

Essential Responsibilities
  • Design and develop digital CMOS circuits, digital subsystems, and reusable IP for advanced semiconductor applications, including control, interface, timing, calibration, and signal-processing functions.
  • Own digital IC development from microarchitecture and RTL implementation through functional verification, synthesis, timing closure, physical implementation, tapeout, and silicon validation.
  • Develop and execute verification strategies using simulation, assertions, coverage, and regression methodologies to ensure functional correctness and robust operation across intended use conditions.
  • Perform and support synthesis, static timing analysis, clock/reset design, power analysis, design-for-test, and physical implementation activities, including post-layout verification and design signoff.
  • Optimize digital architectures for power, performance, area, reliability, and operating-temperature requirements, including cryogenic operating conditions where applicable.
  • Collaborate with PDK, device modeling, technology, analog, layout, and EDA teams to evaluate digital design methodology, libraries, timing models, design rules, and implementation flows for emerging technologies.
  • Define silicon test and characterization requirements, analyze measured data, debug digital functionality and timing issues, and correlate silicon behavior with pre-silicon models and simulations.
  • Lead technical design reviews, document design methodology and results, mentor engineers, and collaborate with cross-functional internal and external teams to enable customer and technology solutions.
Other Responsibilities
  • Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.
Required Qualifications
  • Education
    - Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, Microelectronics, or a related field.
  • Experience
    - Minimum 5 years of relevant digital integrated circuit or ASIC design experience.
  • Skills
    - Demonstrated experience with RTL design and verification using Verilog, System Verilog, VHDL, or equivalent hardware-description languages.
  • Skills
    - Experience with ASIC design flows including synthesis, static timing analysis, clock/reset methodology, design-for-test, physical implementation, timing closure, and signoff.
  • Skills
    - Strong understanding of…
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