Cryo CMOS Analog Design Engineer

Global Foundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, Global Foundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit

Global Foundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, Global Foundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit

Global Foundries is seeking a Senior Analog Design Engineer to develop advanced analog and mixed-signal integrated circuits and reusable IP for emerging semiconductor applications, including cryogenic CMOS and quantum systems. This role will drive designs from circuit architecture through tapeout and silicon validation while partnering closely with technology, PDK, modeling, and test teams.

• Design and develop high-performance analog and mixed-signal CMOS circuits and reusable IP, including amplifiers, bias and reference circuits, regulators, data converters, oscillators, PLLs, clocking circuits, and drivers.
• Own circuit development from architecture and transistor-level design through simulation, layout supervision, physical verification, tapeout, silicon characterization, and design-to-measurement correlation.
• Perform comprehensive circuit analysis across process, voltage, and temperature, including Monte Carlo/mismatch, noise, stability, linearity, timing, and post-layout parasitic simulations.
• Optimize circuit performance across operating temperature ranges, including cryogenic conditions, power constraints, process variation, device behavior, and layout-dependent effects.
• Collaborate with device modeling and PDK teams to assess model accuracy, identify model or design-rule gaps, and provide circuit-level feedback supporting cryogenic and advanced PDK development and validation.
• Drive analog layout requirements and reviews for device matching, common-centroid structures, shielding, isolation, parasitic management, signal integrity, power integrity, and design for manufacturability.
• Define silicon test structures and characterization plans, analyze measured data, debug performance issues, and correlate hardware results with pre-silicon simulation and compact models.
• Lead technical design reviews, document design methodology and results, mentor engineers, and collaborate with cross-functional internal and external teams to enable customer and technology solutions.

• Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.

• Education
  - Bachelor’s degree in Electrical Engineering, Microelectronics, Computer Engineering, Applied Physics, or a related field.
• Experience
  - Minimum 5 years of relevant analog or mixed-signal integrated circuit design experience.
• Skills
  - Demonstrated experience taking analog or mixed-signal circuits through schematic design, simulation, layout, DRC/LVS, parasitic extraction, tapeout, and silicon validation.
• Skills
  - Strong knowledge of CMOS analog design fundamentals, including device physics, noise, matching, feedback, stability, frequency response, process variation, and PVT/Monte Carlo analysis.
• Skills
  -…