ASIC Engineer, Performance Architecture and Modeling; University Grad

Meta's Silicon Engineering organization is building custom silicon solutions that power the infrastructure underpinning Meta's AI and data center workloads  an ASIC Engineer specializing in architecture, performance and modeling, you will define and drive the architectural performance analysis, pre-silicon modeling, and microarchitectural exploration of custom ASICs designed for Meta's infrastructure. In this role, you will establish functional and performance modeling methodologies and long-term silicon roadmap strategy, as well as develop and analyze workloads, partnering with architecture, design, and software teams to ensure Meta's infrastructure silicon meets the demanding throughput, latency, and efficiency targets required C Engineer, Performance Architecture and Modeling (University Grad) Responsibilities:

Drive microarchitectural exploration and trade-off analysis across compute, memory subsystem, interconnect, and I/O domains to inform silicon architecture decisions

Define and own the performance modeling strategy for custom infrastructure ASICs, including development of cycle-accurate and transaction-level simulation environments

Develop and maintain C++ models of AI chip IPs and subsystems for architecture exploration, performance analysis, and software development

Develop low-level workloads and kernels for machine learning training and inference applications

Establish performance analysis methodologies, benchmarking frameworks, and bottleneck identification techniques across the full ASIC pipeline

Collaborate with architecture, RTL design, and physical design teams to translate performance requirements into implementable microarchitectural specifications

Partner with software and systems teams to co-optimize workload scheduling, firmware, and driver behavior against silicon performance characteristics

Lead cross-functional technical reviews and communicate performance modeling results and architectural recommendations to engineering leadership

Define long-term performance modeling infrastructure roadmaps, including tooling, automation, and simulation platform investments

Mentor other engineers on performance modeling techniques, simulation methodology, and microarchitectural analysis best practices

Identify and resolve performance gaps between modeled and measured silicon behavior through structured root-cause analysis and model calibration

Minimum Qualifications:

Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta Currently has, or is in the process of obtaining a Master's or PhD degree in Computer Science, Computer Engineering, Electrical Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta Proficiency in C++ and Python for developing simulation models, automation frameworks, and performance analysis tools

Experience in ASIC performance modeling, microarchitectural analysis, or pre-silicon simulation for custom silicon or SoC designs

Experience with the performance analysis of data center, AI accelerator, or high-performance computing workloads on custom silicon

Experience developing cycle-accurate or transaction-level performance models using C++ and SystemC for complex digital systems, including processors, memory subsystems, or high-speed interconnects

Experience defining microarchitectural specifications and driving cross-functional alignment across architecture, RTL, and physical design teams

Experience with assembly programming languages, and with compiler technologies

Preferred Qualifications:

Experience developing Python-based automation pipelines for simulation orchestration, regression testing, and performance data analysis

Experience with AI numerics, data types, math functions, and precision/accuracy analysis

Experience building or scaling performance modeling infrastructure for hyperscale data center ASICs, including network, storage, or AI inference accelerator designs

Experience writing and optimizing compute/collective kernels in CUDA or equivalent GPU programming frameworks

Familiarity with post-silicon performance validation and model-to-hardware correlation methodologies

Experience with hardware description languages (e.g., System Verilog, VHDL) and simulation environments used in ASIC development flows

Experience with ML domain knowledge including GenAI inference and…