CPU Design & Verification Engineer — College Grad Design Verification Santa Clara​/Hybrid

Nuvacore is building a ground-up, high-performance, low-power CPU for next-generation compute workloads. We are seeking new college graduates to join our CPU team, contributing to either Design Verification (DV) or RTL/micro-architecture design. You'll work shoulder-to-shoulder with architects, RTL designers, and verification engineers across units including fetch, decode/rename, scalar execute, fp/vector execute, load/store, memory management/TLB, prefetching, debug/trace, system/IO, and the multi-level cache subsystem — helping build and prove out a CPU that targets industry-leading power, performance, and area.

Depending on your interests and team placement, you'll contribute to one or both of the following:

• Help build test plans, environments, stimulus generators, checkers, transactors, and coverage that exercise the CPU pipeline end to end.
• Write and debug directed and random tests in assembly, C, or random instruction sequences (RIS) to expose corner cases such as speculation, hazards, flushes, and retirement ordering.
• Partner with architects to correlate RTL against performance models and help identify throughput, stall, and branch-prediction issues.
• Contribute to functional coverage monitors and help analyze metrics toward test plan closure.
• Work with architecture and RTL teams to root-cause failures and support emulation, FPGA, and silicon bring-up.
• Contribute to micro-architecture development, working with the performance modeling team to help converge early designs into detailed specifications.
• Develop and refine RTL targeting power, performance, area, and timing goals.
• Support verification efforts including testbench development, formal methods, and simulation/emulation.
• Assist in performance exploration and correlation, working with performance architecture and verification teams.
• Collaborate with the physical design team to help meet timing, power, area, DFT, and reliability goals.

• BS or MS in Electrical/Computer Engineering, Computer Science, or equivalent practical experience (recent or upcoming graduate).
• Coursework or project experience in digital logic and computer architecture — pipelines, out-of-order execution, branch prediction, or similar topics.
• Proficiency in C/C++, System Verilog, and/or Verilog, plus familiarity with a scripting language (Python preferred; Perl a plus).
• Exposure to functional verification concepts (test benches, checkers, coverage) or RTL design/coding, through coursework, internships, or personal projects.
• Strong fundamentals in CPU micro-architecture concepts.

• Internship or project experience in CPU/complex digital design, verification, or RTL development.
• Exposure to RISC-V, ARM
  64, or x86 ISA and their impact on micro-architectural choices.
• Experience with assembly-level programming or writing tests in assembly.
• Familiarity with constrained-random verification, coverage-driven closure, or assertions/formal verification.
• Exposure to emulation/FPGA environments, waveform debug, or silicon bring-up.
• Interest or coursework in one or more specialization areas: instruction fetch, branch prediction, decode/rename, out-of-order execution, load/store, cache and memory subsystems, memory coherence, or power management.
• Strong preference for being located at one of our main offices in Austin or San Jose.