Cellular ASIC Design Engineer

Apple is seeking a Cellular ASIC Design Engineer to join its Hardware Technologies group, where innovation and collaboration drive the development of next-generation cellular chips and system-on-chips (SoC). This role focuses on creating high-performance, power-efficient designs that enhance Apple products and services, contributing to the company's mission of delivering groundbreaking technology.

Responsibilities:

• Develop and optimize design and implementation methodologies for integrated circuits, focusing on area efficiency, power optimization, and design technology co-optimization.
• Establish design guidelines and standards for synthesis, place-and-route, timing closure, and signoff processes.
• Develop and optimize EDA tool flows, including synthesis, place-and-route, and signoff tools.
• Drive timing convergence process improvements to enhance design power, performance, and area (PPA) and yield.
• Create and maintain design flows, scripts, and automation tools to improve productivity and reduce turnaround time.
• Identify utilization bottlenecks in physical design and develop solutions to improve utilization.
• Collaborate with physical design teams for timing closure and validation of flow scripts/tools.
• Perform design technology co-optimization analysis and conduct Spice simulations for validation.
• Conduct timing package validation and in-depth analysis of design databases and silicon validation data.
• Develop and implement power optimization methodologies, including voltage scaling and dynamic techniques.
• Collaborate with technology and IP teams to enhance efficiency in custom and semi-custom IP development.
• Support advanced process technology bring-up from PDK to VLSI design production.
• Drive improvements in Design for Test (DFT) methodologies and strategies.
• Stay updated on industry trends and emerging technologies to enhance design methodologies.

Qualifications:

• Solid understanding of Physical Design challenges.
• Proficiency with synthesis, place and route tools, and timing closure processes.
• Experience with EDA tools and methodologies for ASIC design.
• Strong programming skills in Python, Perl, TCL, Unix shell, and C/C++.
• Experience with machine learning modeling for design optimization.

Skills:

• Expertise in design flow and methodology development.
• Strong analytical skills for design technology co-optimization.
• Proficient in power and performance optimization techniques.
• Ability to collaborate effectively with multi-functional teams.
• Strong problem-solving skills and attention to detail.