ASIC Engineer, Design Test

Meta is building custom silicon to power the next generation of infrastructure and computing platforms. As an ASIC Engineer specializing in Design for Test (DFT) on the Infrastructure Silicon team, you will architect and implement testability solutions for complex, high-performance ASICs deployed at scale across Meta's data center infrastructure. In this role, you will define DFT strategies from RTL through silicon bring-up, ensuring manufacturability, diagnosability, and high fault coverage across large, multi-billion gate designs.

You will collaborate closely with design, physical implementation, and validation teams to deliver silicon that meets aggressive quality and time-to-market targets.

ASIC Engineer, Design for Test Responsibilities:

Define and implement comprehensive DFT architectures including scan insertion, ATPG, MBIST, LBIST, and boundary scan for large-scale infrastructure ASICsDevelop and drive DFT methodology and flows from RTL through tape-out, including scan compression, test point insertion, and clock domain handling

Generate, simulate, and validate ATPG test patterns to achieve target fault coverage across stuck-at, transition, path delay, and cell-aware fault models

Collaborate with physical design teams to ensure DFT structures meet timing, area, and power constraints during implementation

Partner with silicon validation and manufacturing test teams to define ATE test programs and support post-silicon debug and diagnosis

Perform DFT sign-off including fault coverage analysis, test coverage reporting, and DRC/LVS compliance for testability structures

Develop and maintain DFT scripts and automation to improve flow efficiency, reduce manual effort, and enable reuse across chip generations

Support silicon bring-up activities by analyzing failure data, performing scan diagnosis, and identifying root causes of manufacturing defects

Contribute to DFT roadmap planning by evaluating emerging test methodologies and recommending improvements to Meta's silicon test strategy

Provide technical guidance to peers on DFT best practices, design partitioning for testability, and cross-functional trade-off decisions

Minimum Qualifications:

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience6+ years of experience in DFT engineering for complex ASIC or SoC designs, including scan insertion, ATPG pattern generation, and MBIST implementation

Experience with industry-standard DFT EDA tools for scan compression, ATPG, and memory test (e.g., Tessent, Synopsys DFT Compiler, TetraMAX)
Experience achieving high fault coverage targets across multiple fault models (stuck-at, transition delay, cell-aware) on multi-million gate designs

Experience supporting silicon bring-up and manufacturing test, including ATE correlation and scan-based diagnosis

Experience scripting in Tcl, Python, or Perl to develop and maintain DFT automation flows

Preferred Qualifications:

Familiarity with IEEE 1500, IEEE 1687 (IJTAG), or IEEE 1149.1 boundary scan standards and their application in infrastructure ASICsBackground in post-silicon failure analysis and yield improvement using scan diagnosis and statistical defect modeling

Experience with at-speed test methodologies including launch-on-capture and launch-on-shift for timing-critical paths

Experience with DFT architecture for high-speed Ser Des interfaces, mixed-signal IP, or hierarchical test integration in large multi-die or chiplet designs

About Meta:

Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and Whats App further empowered billions around the world. Now, Meta is…