Principal Physical Design Engineer​/Physical Design – ACE

## Principal Physical Design Engineer / Physical Design – ACE USApply:
Austin (Oakhill, Office):
Full time:
Posted Today:
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- ** Role Summary
** We are seeking an experienced  Digital Designer for
** SoC Implementation / Physical Design
** for advanced semiconductor products. This role will own end-to-end physical design execution across complex designs, driving delivery from RTL to silicon for cutting-edge technology nodes.

The ideal candidate demonstrates  deep technical expertise to implement a given design on silicon with optimized quality and meeting PPA targets.
** Key Responsibilities
**** 1. End-to-End Physical Design Ownership
*** Lead Physical design execution including floor planning, synthesis, place & route, CTS, routing, STA, PDN, PDV and signoff.
* Drive timing, power, IR/EM, and physical verification closure to achieve tapeout readiness.
* Deliver optimized PPA (Power, Performance, Area) across complex designs.
* Aligns with internal expectations of implementing designs on silicon with optimal quality, PPA, and cost efficiency
** 2. Team Leadership & Organization Development
*** Participate in mentoring and career development.
* Role-Model  execution discipline, review mechanisms, and performance tracking.
* Interface with senior leadership for status reporting, escalation, and decision-making.
** 3. Technical Strategy & Innovation
*** Define and deploy next-generation physical design methodologies.
* Drive automation, flow optimization, and tool innovation.
* Lead adoption of advanced node technologies (5nm and beyond).
* Improve scalability, productivity, and design quality through methodology enhancements.
** 4. Cross-Functional & Ecosystem Engagement
*** Collaborate with architecture, RTL, verification, and product teams to ensure design convergence.
* Interface with EDA vendors and IP providers for tool and flow optimization.
* Support post-silicon bring-up, yield improvement, and production ramp activities.
** Core Technical Expertise
*** Full RTL-to-GDSII implementation flow (Cadence and/or Synopsys tool sets)
* Floor planning, synthesis, PNR, CTS, routing
* STA and signoff methodologies
* Physical verification (DRC/LVS/ERC)
* Advanced node implementation (≤ 16nm / 5nm)
* Low power design (UPF/CLP)
* Scripting in Python, TCL, and Perl
** Required Qualifications
*** Bachelor’s or Master’s in Electrical / Electronics Engineering or related field
* 10+ years of experience in ASIC / SoC physical design
* Strong knowledge of industry EDA tools (Synopsys, Cadence flows)
* Strong communication skills
** Preferred Qualifications
*** Experience in high-reliability So Cs
* Exposure to AI-driven design methodologies and automation
** Why This Role Matters
*** Own delivery of flagship SoCs at advanced nodes
* Drive innovation in physical design methodologies
* Direct impact on silicon success and product competitiveness