Senior ASIC DFT Engineer – Test
Listed on 2026-10-18
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Engineering
Test Engineer, Hardware Engineer
Meta is seeking an ASIC Engineer specializing in Design for Test (DFT) to architect testability solutions for large-scale infrastructure ASICs used in data center hardware. You will drive DFT strategies from RTL to tape-out, implement scan insertion, ATPG patterns, MBIST, and LBIST, and ensure high fault coverage across multiple models.
You will collaborate with design, physical, and validation teams to balance timing, area, and power while supporting post-silicon debugging and ATE programs.
We would love to welcome a new Senior ASIC DFT Engineer – Test & Bring-Up to our team in Austin, TX, United States.
Full responsibilities and requirements are described in the listing above.
Learn more about the Senior ASIC DFT Engineer – Test & Bring-Up role in the description above.
We appreciate your interest in this position.
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