Senior Design Verification Engineer

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets.

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The Wireless PHYMAC teamis responsible for designing the digitalcomponentsof Silicon Labs’low powerenergy-efficient wireless products. Our team focuses on building efficient, high-performance digital systems that enable wireless connectivity across applications such as smarthome, industrial IoT, and smart cities.

The teamoperatesin a highly collaborative and cross-functional environment, working closely with system architects, analog/RF designers, firmware engineers, and product teams to deliver robust and scalable wireless solutions. By working at the intersection of digital design and wireless systems, the team plays a critical role in advancing the future of connected devices.

As aSenior Design Verification Engineer, you willbe responsible for ensuring the functional correctness and performance of digital modem designs used in Silicon Labs’ low-power wireless products. You will work closely with design, architecture, and system teams to develop verification strategies, build robust test environments, and debug complex issues across the PHY/MAC layers. This role offers the opportunity to contribute throughout the product lifecycle—from early design through silicon bring-up—while working oncutting-edge wireless technologies that power next-generation connected devices.

• Define and execute verification strategies for digital modem designs across key wireless use cases
• Develop andmaintainscalable verification environments using
  
  System
  
  Verilog/UVM or similar methodologies
• Create test plans,test benches, and stimuli to achieve high functional and coverage closure
• Debug and analyze design issues, working closely with design and architecture teams to resolve them
• Track and drive functional and code coverage to ensure verification completeness
• Collaborate cross-functionally with firmware, validation, and system teams to ensure correct system behavior
• Support silicon bring-up and correlate pre-silicon verification with post-silicon results
• Continuously improve verification methodologies, tools, and automation workflows

• BSEE/CE or a related field
• Solid understanding of digital design fundamentals and verification concepts
• 3-6 years of experience in digital design verification, with a focus on modem or wireless PHY designs preferred
• Experience with
  
  System
  
  Verilogand UVM or similar verification methodologies
• Strong debugging skills with experience analyzing simulation results andidentifyingroot causes
• Familiarity with scripting languages such as Python or Perl for automation
• Basic understanding of wireless communication systems or digital signal processing concepts
• Strong problem-solving skills and ability to work effectively in a collaborative team environment

• Experience verifying wireless standards such as BLE, Wi-Fi, Zigbee, or similar technologies
• Experience with advanced verification techniques such as constrained-random, coverage-driven verification, andSystem
  
  Verilogassertions (SVA)
• Familiarity with C/C++ or MATLAB for algorithm modeling and reference model development
• Experience with mixed-signal or…