Senior RTL Designer – L1 Accelerator IP; Hybrid
Listed on 2026-10-18
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Engineering
Hardware Engineer, Systems Engineer, Electronics Engineer, Electrical Engineering
Ericsson’s Accelerator IP team in Austin, TX is seeking a Senior RTL Design Engineer to own the microarchitecture of next-generation L1 accelerators from concept to silicon. You will translate DSP/FEC algorithms into high-performance System Verilog, balance power, area and throughput, and lead major IP blocks through specification, microarchitecture, RTL, and delivery.
Join a lean, high-impact team where your designs ship into world-class telecom products and your contributions drive innovation
We have an opening for a Senior RTL Designer – L1 Accelerator IP (Hybrid) in Austin, TX, United States within Engineering.
We are seeking a motivated Senior RTL Designer – L1 Accelerator IP (Hybrid) to join Ericsson in Austin, TX, United States.
Consider building your career as a Senior RTL Designer – L1 Accelerator IP (Hybrid) at Ericsson.
The Senior RTL Designer – L1 Accelerator IP (Hybrid) position in the Engineering field is open for applications.
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