SoC STA Design Engineer - Timing Signoff Lead

NXP Semiconductors in Austin, TX seeks an experienced SoC STA engineer to own end-to-end timing signoff across complex designs. You will drive constraint creation, validate with frontend, IP, and DFT teams, and collaborate with implementation to close timing at advanced nodes.

The role emphasizes scripting (Python, TCL, Perl) for timing ECOs, AI-assisted automation, and continuous methodology improvements to boost design quality and productivity.

We are looking to fill the SoC STA Design Engineer
- Timing Signoff Lead position at NXP Semiconductors NV in Austin, TX, United States.

The following opening is for a SoC STA Design Engineer
- Timing Signoff Lead with NXP Semiconductors NV.

Our group is growing, and we are hiring a SoC STA Design Engineer
- Timing Signoff Lead in Austin, TX, United States.

This opening is for the SoC STA Design Engineer
- Timing Signoff Lead role at NXP Semiconductors NV.