Satellite Chip Verification Engineer - UVM & Verilog
Listed on 2026-10-18
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Engineering
Test Engineer, Electronics Engineer, Quality Engineering
Amazon Leo in Austin, TX is seeking a Junior Design Verification Engineer to help define and implement digital SOC verification for high‑speed satellite communications. You will build state-of-the-art verification environments and collaborate with modem, DSP, and processor teams to validate RTL against Matlab/C models.
The role emphasizes developing automated regression workflows, writing detailed test plans, and participating in System Verilog/Verilog ASIC validation using UVM.
Consider building your career as a Satellite Chip Verification Engineer - UVM & Verilog at Amazon Inc.
As a Satellite Chip Verification Engineer - UVM & Verilog, you will play an important part at Amazon Inc. in Austin, TX, United States.
We invite applications for the Satellite Chip Verification Engineer - UVM & Verilog position located in Austin, TX, United States.
The following opening is for a Satellite Chip Verification Engineer - UVM & Verilog with Amazon Inc.
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