Emulation​/Debug Engineer

Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group  ASICS Engineering General

Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.

Qualcomm's Emulation Team is part of the central SoC digital hardware organization responsible for the overall development and support of SoC pre-silicon platforms. The Emulation team works closely with architects, designers, verification engineers, software engineers, and customers. The team is currently seeking candidates with experience in the following technical disciplines, languages, and methodologies:

Emulation Platforms (FPGA Prototyping, Veloce, Palladium), Emulation tools (Synthesis, Place and Route, Constraints, Clocking, Timing Closure), System Debug (Waveform generation and Content Debug support)
SoC Functionality (CPU/DSP Core, Multimedia, IO, Peripherals, DDR, Modem, Bus Protocols)
Preferred Requirements :5+ years of experience working in emulation and silicon environments. Candidates are expected to have experience in:

Design, development, and deployment of uniform global methodologies for emulation build generation and debug across FPGA based emulation platforms of various configurations

Cross-site collaboration, vendor engagements, and executive communication

Pre-silicon prototyping for new SoC designs, including pre-silicon enablement and bring-up Bring-up of new FPGA emulation/prototyping hardware and software

Debugging low level software and hardware issues

Debug tools including JTAG and kernel debuggers

Validation and debug of digital circuits CPU and SoC architectures, with solid understanding of SoC building blocks (interconnects, power management, PMIC, NoC, peripherals)
Basic understanding of power and performance

Expertise in Verilog / System Verilog Experience  with C programming Scripting:
Proficient in Python, TCLFPGA Expertise:
Xilinx/Intel FPGAs, Tools, and timing closure techniques

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

ORMaster's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.

ORPhD in Science, Engineering, or related field.

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