Principal Design Verification Engineer – CPU Subsystem

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SiFive is looking for a Principal Design Verification Engineer to lead verification strategy and execution for a high-performance CPU subsystem spanning both out-of-order CPU core development and cache-coherent interconnect/subsystem behavior. This is a Principal individual-contributor role for an engineer who can define architecture-aware verification strategy, identify risks early, solve the hardest subsystem-level problems, and raise verification quality across a broader organization.

The role bridges key CPU and uncore domains, including high-performance OoO core areas such as Frontend, Midcore, Load-Store Unit, and Hardware Prefetch, together with coherent data movement, protocol correctness, ordering, flow control, quality-of-service behavior, and subsystem integration across interconnect fabrics and bridge paths. You will work closely with architecture, RTL, formal, performance, and design verification teams to ensure design intent is captured correctly, debugability is considered early, and signoff quality is achieved with strong technical judgment and scalable methodology.

• Lead verification strategy and execution for high-performance CPU subsystem development, with scope spanning OoO core microarchitecture and coherent interconnect/subsystem behavior.
• Own verification planning, execution, debug, coverage analysis, and closure from block level through subsystem integration and signoff.
• Define verification strategies for complex CPU behaviors including branch prediction, instruction fetch, issue/dispatch behavior, pipeline interactions, load/store ordering, hazard handling, memory consistency, and hardware prefetch correctness.
• Define verification strategy and closure criteria for coherent traffic, protocol correctness, ordering rules, back pressure, buffering behavior, arbitration, QoS, and error handling across cache-coherent interconnect paths.
• Drive verification across interface boundaries, bridges, and protocol adaptation paths, including conversion, buffering, and related subsystem-level data movement behavior.
• Develop high-value checkers, scoreboards, assertions, stimulus strategies, and coverage models that expose corner cases and improve bug-finding efficiency across both core and uncore verification problems.
• Apply the right verification method for the problem, using simulation, formal techniques, and emulation to improve quality, accelerate turnaround, and…