CPU RTL Design Engineer

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THE ROLE:

As a CPU Core RTL Design Engineer, you will help design and optimize next-generation, high-performance processor cores within the central core RTL team, supporting products across client, server, and AI platforms. Working with architecture, performance, verification, and physical design partners, you will contribute to the development of core pipeline logic and microarchitecture features. Depending on your experience and technical background, opportunities may align with areas such as load/store, decode, or other CPU core subsystems.

Your work will contribute to the performance, power efficiency, and scalability of future CPU designs while addressing complex processor design challenges.

THE PERSON:

You are an engineer with demonstrated experience solving complex digital design or processor architecture problems and an interest in developing efficient, high-performance designs. You collaborate effectively across teams, communicate technical concepts clearly, and work effectively both independently and collaboratively. You can evaluate design alternatives and technical trade-offs while considering performance, power, area, and timing requirements.

KEY RESPONSIBILITIES:

Design and implement RTL for CPU core pipeline components and related logic

Contribute to microarchitecture definition for next-generation processor cores

Collaborate with architecture, verification, performance, and physical design teams to deliver optimized designs

Analyze and improve performance, power, area, and timing characteristics

Support design verification, synthesis, timing closure, and physical design efforts

Investigate and resolve pre-silicon and post-silicon issues

Partner with cross-functional teams to evaluate design alternatives and align on technical trade-offs Contribute to scalable RTL methodologies, libraries, tools, and engineering best practices

PREFERRED EXPERIENCE:

Candidates are encouraged to apply even if they do not have experience in every area listed below.

Experience with Verilog/System Verilog RTL development in CPU, SoC, ASIC, or comparable digital design environments

Understanding of modern CPU architecture, including out-of-order processor concepts

Experience with logic design and high-performance processor pipeline development

Experience with load/store, decode, execution, scheduling, or other CPU core subsystems

Knowledge of power-efficient and low-power design techniques, including timing and power optimization

Familiarity with synthesis, place-and-route, static timing analysis, and timing closure

Experience debugging and optimizing designs in collaboration with performance and verification teams

Exposure to multiple stages of the product development lifecycle, including architecture, implementation, verification, or post-silicon debug

Familiarity with physical design, scripting such as Python or Tcl, and concepts such as DFT, clocking, reset, and power management

Relevant experience in processor, accelerator, SoC, or other complex digital design environments may also be considered ACADEMIC CREDENTIALS:

Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience

This…