Sr. Package Engineer, Annapurna Labs - AI Silicon Packaging

Annapurna Labs designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world.

The Package Technology Development team within Annapurna Labs is building the packaging, substrate/PCB, interposer, and assembly technologies for the next-generation Trainium AI accelerators. The team works at the intersection of silicon, package, board, system, and rack, partnering closely with design, manufacturing, supply chain, and reliability teams to bring bleeding-edge AI systems from concept to volume production.

Key job responsibilities
- Define and drive package technology development across architecture, design, materials, processes, yield, warpage, reliability, and system-level integration for next-generation Trainium systems, from early concept through volume production.

- Partner with OSATs and component/material/equipment suppliers on capability validation, test vehicle development, qualification, TGA, FMEA, risk retirement, root-cause analysis, and corrective/preventive actions
- Evaluate tradeoffs across performance, cost, yield, manufacturability, warpage, thermal performance, and reliability to guide technology decisions and qualification strategies.

- Represent the package technology team in cross-functional design reviews, sign-off milestones, and program checkpoints with silicon, board, system, and supply chain teams.

- Identify opportunities for novel packaging architectures and process simplifications to reduce cost, improve yield, and accelerate time-to-market.

Basic qualifications
- Experience coordinating between technical teams, peers and business stakeholders
- Bachelor's in Materials Science, Mechanical Engineering, Electrical Engineering, Chemical Engineering, or 10+ years of industry experience in a related field
- Expertise in at least one: substrate/PCB technology, interposer technology, or package and board assembly technology
- Track record of driving technology development from concept through qualification

Preferred qualification - Master's in Materials Science, Mechanical Engineering, Electrical Engineering, Chemical Engineering, or 8+ years of industry experience in a related field
- Or PhD in Materials Science, Mechanical Engineering, Electrical Engineering, Chemical Engineering, or 6+ years of industry experience in a related field
- Familiarity with package-level SI/PI concepts (impedance control, PDN design, crosstalk-aware routing) sufficient to collaborate with SI/PI engineers

- Experience with substrate/PCB architecture, materials, processes, yield, warpage, and DFM for advanced systems, including HDI, microvias, fine-line/space, and high-speed/power routing

- Experience with interposer fabrication and DFM for 2.5D/3D systems (e.g., CoWoS-R/L), including RDL, TSV, silicon bridges, microbumps, and package floor planning

- Experience with package and board assembly processes, including flip-chip, thermal compression bonding, hybrid bonding, underfill, molding, TIM, and fine-pitch assembly. Co-packaged optics (CPO) experience is a plus.

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