ASIC DFT Engineering Technical Leader

The application window is expected to close on: 12/21/2026

Meet the Team The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow.

Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.

Your Impact You will be in the Silicon One development organization as an ASIC Implementation Technical Lead with a primary focus on Design-for-Test. You will work with Front-end RTL teams and backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team, you will also be involved in crafting groundbreaking next-generation networking chips.

You will help lead to drive the DFT and quality process through the entire Implementation flow and post-silicon validation phases with additional exposure to physical design signoff activities. Ability to work with ATE engineers on pattern translation and validation.

Minimum Qualifications Bachelor’s degree in Electrical or Computer engineering and 8+ years of experience, or Master’s degree in Electrical Engineering or Computer Engineering and 6+ years of experience, or PhD in Electrical Engineering or Computer Engineering + 3 years of experience

Prior experience with ATPG and EDA tools like Test Max or Tetramax or Tessent or similar tool sets Prior experience working with Gate level simulation, including timing-based simulations with SDF, debugging with VCS and other simulators

Prior post-silicon validation and debug experience

Prior experience with scan insertion

Preferred Qualifications Verilog design experience – developing custom DFT logic & IP integration; familiarity with functional verification Prior experience with EDA tools like Tessent Prior experience with Jtag protocols (p1500, p1687)
Prior experience with SSN Scripting skills:
Tcl, Python/Perl Prior experience with test static timing analysis constraints development and timing closure Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada:

The starting salary range posted for this position is $ to $ and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.

Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For…