DPU Networking Architect, Infrastructure Silicon

Meta’s Infrastructure Silicon organization designs custom silicon that powers our data center infrastructure — SmartNICs/IPUs/DPUs, AI accelerators, and networking ASICs. We are looking for a Data Processing Unit (DPU) Network Architect to own how our DPUs handle networking: packet processing and offloads, network virtualization and overlays, RDMA and storage transports, and inline security. You’ll decide how the networking datapath is built and where each function belongs – in hardware, in firmware, or in host software – define how software programs it, and carry those decisions from early path-finding through implementation and silicon bring-up.

You’ll work hand in hand with the firmware, driver, and RTL teams, backing your calls with performance and PPA analysis where deeper study is needed.

DPU Networking Architect, Infrastructure Silicon Responsibilities:

• Architect the Networking datapath for our DPUs – packet processing and offloads, Network virtualization and overlays, RDMA and storage transports, and inline security – from early path-finding through silicon bring-up
• Decide what runs in the datapath engines, what runs in firmware, and what stays in host software, and design the interfaces between them
• Define how software programs and controls the datapath – match-action tables, rule and flow programming, register and descriptor interfaces, and the offload interfaces firmware and drivers build on
• Work closely with firmware, driver, and software teams so the datapath and its interfaces are clean, efficient, and genuinely usable, and evolve them as needs change
• Work closely with design, DV, and PD teams on feature definition and PPA tradeoff
• refine architecture to meet the design and PD constraints. Define architecture to maximize DV complexity including defining specific features to help ease DV
• Weigh the performance, power, and area trade-offs behind your choices and back them with data, partnering with performance modeling where deeper analysis is needed
• Support Design, DV and PD to resolve interface and integration issues as they come up. Support post-silicon bring-up of the Networking functionality

Minimum Qualifications:

• 8+ years of relevant industry experience architecting Networking datapaths and packet-processing pipelines and their hardware/software interfaces for NIC/DPU or comparable ASICs
• Experience with SmartNIC/IPU/DPU architectures and their usages:
  Network virtualization, storage disaggregation, overlay networking, virtual switch, firewall/ACLs, and PSP gateways, including offload mechanisms
• Experience with datacenter Networking technologies and protocols such as Ethernet, IPv6, TCP/UDP, Geneve, PSP, and SRv6, including offload mechanisms for TCP segmentation, reassembly, checksum, and receive-side scaling
• Experience with RDMA and storage protocols and fabrics, including RoCEv2 and NVMe/NVMe-over-Fabric (TCP and RDMA)
• Experience with congestion control (e.g., DCQCN) and emerging transports such as UET and comparable next-generation RDMA transports
• Experience with on-chip scheduling and arbitration architectures and quality-of-service mechanisms — transaction/packet schedulers, arbiters, traffic shapers, and rate limiters (meters/policers, token buckets) — and their impact on latency, fairness, bandwidth partitioning, and throughput
• Experience with datacenter network topologies and fabric architectures (e.g., Clos/fat-tree, rail‑optimized fabrics) and their performance implications, including over subscription, ECMP/load balancing, and end‑to‑end latency and congestion behavior
• Experience with symmetric and asymmetric cryptography concepts and inline data encryption (e.g., IPSec, PSP)
• Experience with domain‑specific dataplane languages such as P4
• Experience with data center…