ASIC Design Engineer, Kuiper ASIC Design

Amazon Leo is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world.

Export Control Requirement: Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.

• RTL design and development of custom blocks.
• Integration of large subsystems.
• Gate level simulation: develop and maintain comprehensive gate-level simulation test plans for verifying ASIC functionality and timing; analyze results, debug logic errors, propose solutions; work closely with design and verification engineers to validate fixes and ensure design closure.
• Facilitate seamless integration across Firmware, RTL, Platform Software, and Platform Drivers.
• Develop debug tools: RTL Emulation, silicon bring-up, and functional validation.

• Work closely with the system architects to develop world‑class SOC and IP blocks that meet power, area, and performance targets.
• Define, configure, and integrate SoC subsystems.
• Contribute to the SoC floor‑planning effort.
• Define and develop any necessary support logic.
• Configure, instantiate, and integrate third‑party IP blocks.
• Understand low‑power design and the impact of DFT on the blocks.
• Perform initial synthesis and timing analysis.
• Assist the verification team in unit verification, including test‑plan development.
• Assist with debug and bring‑up.

Be part of Amazon LEO’s sub‑team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. This is a unique opportunity to define a wireless solution with few legacy constraints. The team works with customer requirements and wireless system teams to define modems, high‑speed interfaces, embedded processors, and DSP solutions in latest CMOS generation technologies.

• 3+ years of non‑internship professional Verilog RTL development experience.
• 3+ years of programming with at least one Verilog RTL programming language.
• 3+ years of leading design or architecture of new and existing systems.
• 3+ years of digital design experience, preferably in SoC design and implementation.

• 2+ years of full software development life cycle experience, including coding standards, code reviews, source control management, build processes, testing, and operations.
• Master's degree in computer science or equivalent.

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Our compensation reflects the cost of labor across several U.S. geographic markets. The base pay for this position ranges from $104,000/year in our lowest geographic market up to $212,200/year in our highest geographic market. Pay is based on a number of factors including market location and may vary depending on job‑related knowledge, skills, and experience. Amazon is a total compensation company.

Dependent on the position offered, equity, sign‑on payments, and other forms of compensation may be provided as part of a total compensation package, in addition to a full range of medical, financial, and/or other benefits. For more information, please visit  This position will remain posted until filled. Applicants should apply via our internal or external career site.