Principal Design Verification Engineer – CPU Core Frontend

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Job Description:

About the Role Si Five  is looking for a Principal Design Verification Engineer to lead verification strategy and execution for the CPU Core Frontend in a high-performance out-of-order core. This is a senior tech-lead role for an engineer who can define architecture-aware verification strategy, identify microarchitectural risk early, solve the hardest frontend verification problems, and raise verification quality across the broader CPU DV organization.

The primary technical scope of this role is frontend verification, with emphasis on branch prediction, instruction fetch, frontend redirects and recovery, prediction training/update behavior, fetch correctness, and interface interactions across the frontend pipeline. The role requires close partnership with architecture, RTL, performance, and verification teams to ensure design intent is captured correctly and signoff quality is achieved with strong technical judgment and scalable methodology.

Responsibilities Lead verification planning and execution for CPU frontend functionality in a high-performance out-of-order core, with ownership spanning branch prediction and instruction fetch behavior.

Define verification strategy, test plans, checkers, scoreboards, assertions, stimulus strategies, and coverage models for frontend microarchitecture and its corner cases.

Drive verification of branch prediction structures and flows, including direction prediction, indirect target prediction, return prediction, predictor update/training behavior, redirect generation, recovery, and interaction with global history or related predictor state.

Drive verification of instruction fetch behavior, including fetch packet correctness, PC sequencing, fetch ordering, ITLB/translation interactions, exception reporting, cache-related fetch behavior, and redirect handling after misprediction or flush conditions.

Partner with architects and designers from early feature-definition stages to review specifications, identify ambiguity, and improve frontend debugability and verification completeness.

Drive block-level and core-level verification closure for frontend features, including coverage analysis, gap identification, bug triage, and signoff readiness.

Apply the right verification method for the problem, including simulation, formal techniques, and emulation where appropriate for high-risk or hard-to-observe frontend behaviors.

Mentor engineers across the organization and…