Sr. Layout Engineer
Listed on 2026-11-05
-
Engineering
Electronics Engineer, Electrical Engineering, Systems Engineer
Location:
San Jose, CA or remote
Job Description Silicon Brite is seeking an experienced layout engineer that will perform analog & mixed-signal (AMS) IC layout according to engineering specifications and by using the Cadence Virtuoso EDA tool.
Details The ideal candidate(s) will further perform
Design of chip layout and complete set of design verification for various analog mixed-signal circuits (individual blocks to full-chip level).
Manage in-house developed IP library and optimization of layout implementation techniques.
Solid knowledge of Physical verifications, debug, and parasitic extractions including LVS/DRC.
Analyze and review floor planning/schematics with responsible IC designers.
Details The ideal candidate(s) should have the following qualificationsBachelor of Science in Electrical Engineering or equivalent.
At least 15 years of direct experience working with semiconductor companies.
Good understanding of the Cadence EDA toolset.
Basic knowledge of AMS circuits is preferred.
Strong analytical and communication skills.
Self-starter and excellent team player.
The position can be based in San Jose, CA, or a remote location globally.
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).