CPU Physical Design Lead

Location: Bengaluru

CPU Physical Design Lead

Location:

Bengaluru

Experience:

6–10 Years

Role Overview
We are seeking a CPU Physical Design Lead to drive implementation and signoff of high-performance CPU cores/subsystems on advanced technology nodes. You will own backend execution from floorplan through tapeout, working closely with architecture, RTL, STA, DFT, and methodology teams to achieve aggressive PPA targets.
Responsibilities
Lead block/subsystem-level physical design for high-frequency CPU designs.
Own end-to-end implementation: floor planning, power planning, placement, CTS, routing, STA closure, and physical signoff.
Drive timing, power, congestion, IR/EM, and noise convergence across multiple modes/corners.
Develop scalable PD methodologies and automation for advanced-node implementation.
Execute ECO closure and tapeout readiness with strong focus on QoR.
Collaborate cross-functionally with RTL, DFT, power, and integration teams to resolve design bottlenecks.
Mentor engineers and drive technical execution across project milestones.

Required Qualifications
6–10 years of experience in ASIC/SoC physical design with strong CPU implementation background.
Expertise in advanced nodes (7nm/5nm/3nm FinFET technologies preferred).
Deep hands-on experience in:
Floor planning and physical architecture
Timing closure and SI debugging
CTS and clock distribution optimization
IR/EM and power integrity analysis
Physical verification and ECO implementation
Strong knowledge of industry tools including:
Cadence Innovus
Synopsys ICC2
Prime Time
Tempus
Strong scripting skills in Tcl/Python/Perl.
Proven track record of successful tapeouts in complex high-performance designs.
Preferred

Experience with CPU cache, execution pipeline, or top-level integration blocks.
Exposure to low-power and multi-voltage implementation techniques.
Strong debugging mindset with data-driven optimization approach.