ASIC Physical Design and STA Senior​/Lead

Position: ASIC Physical Design and STA Senior/Lead/Staff
Location: Bengaluru

I'm hiring for skilled VLSI engineers from 3-10 years experience in the following domains:

- Synthesis
- Physical Design
- STA
- Physical Verification

Salary Range : 10 - 50 Lakhs/Annum

If you are looking for an exciting role with continuous growth, high salary with mentored learning on the job, then please apply at the earliest.

Reach us at:

Role Description

This is a full-time on-site role for an ASIC Physical Design and STA Senior/Lead/Staff located in Bengaluru. The role involves taking ownership of Synthesis and physical design implementation, including logic synthesis, LEC, CLP, floor planning, placement, clock tree synthesis, and routing.

STA responsibilities include performing Static Timing Analysis (STA), Timing Closure using DMSA/Tweaker and developing and analyzing timing constraints, and working collaboratively with cross-functional teams including verification, logic design, and architecture teams.

Physical verification responsibility includes owning complete PV signoff for an SoC, having good understanding of nanotech node(2nm-40nm) issues and their resolution. You should be able to setup and run DRC, LVS, ERC, Antenna checks at both block and toplevel and be able to debug and resolve design layout issues.

The individual will ensure design meets performance, power, and area requirements while resolving issues related to physical verification and tapeout.

Qualifications

- Proficiency in Innovus, FC, PT, Tweaker, DC, Genus, Calibre, ICV
- Strong Research skills for problem-solving and design optimization
- Analytical skills with attention to detail and an ability to adhere to project timelines