SoC UPF Methodology Engineer

Role Number:
Team:
Hardware

Location:

Austin;
Beaverton;
Cupertino;
San Diego Posted:
Summary Are you passionate about crafting solutions to intricate challenges? Join the Low Power groupat Silicon Technologies and contribute to the development of cutting-edge technology and capabilities for low-power chip design. Your work will fuel Apple’s next-generation chips!

You’ll play a crucial role in exploring AI/ML to design the workflow for the next generation ofUPF. Additionally, you’ll refine our existing UPF framework and ensure its seamless integration and rigorous verification across our mobile products.

You will be part of an exciting silicon design group that is responsible for designing state-of-the-art ASICs.We have an extraordinary opportunity for Power UPF Engineers, who will drive transistor level power ERC sign-off and power intent-UPF implementation & verification on mobile SOCs.Description In this role, your main objective will be to enhance our Unified Power Format (UPF) methodologies, refining power intent specification, execution, and validation to support state-of-the-art mobile SOCs.

Key responsibilities encompass:
• Enhancing power intent coverage via advanced static and dynamic verification techniques.
• Developing tailored UPF solutions to align with unique project requirements.
• Overseeing UPF deployment and sign-off for frontend (FE) and place-and-route (P&R) stages.
• Conducting thorough power intent assessments on custom circuitry.
• Partnering with design and verification teams to troubleshoot and fix UPF-related workflow challenges.
• Integrating AI/ML technologies to optimize UPF processes and methodologies.

Minimum Qualifications A minimum of a bachelor's degree in relevant field and a minimum of 3 years of relevant industry experience

Preferred Qualifications Expertise in UPF implementation and verification.

Proficiency in scripting with languages like Python and Tcl.

Understanding of CMOS power design principles.

Experience applying AI/ML to coding and workflow optimization.

Knowledge of multi-voltage static verification tools (e.g., VSILP/VCLP, CLP).Familiarity with the complete RTL-to-GDSII design flow.

Strong communication abilities for effective collaboration across multidisciplinary teams.

Pay & Benefits At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $150,400 and $277,600, and your base pay will depend on your skills, qualifications, experience, and location.

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including:
Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits

Note:

Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Pay & Benefits At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between…