Senior SoC Physical Design Lead; -Level
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Engineering
Job Description & How to Apply Below
Apple, Inc. in Beaverton, Oregon seeks an experienced chip design engineer to deliver complete chip design from netlist to tapeout in a highly visible role.
You will collaborate with FE and physical design teams to define architecture, drive floor planning, clock/power distribution, IP integration, and manage place and route, timing convergence, and issue resolution. Candidates should have a BS and 10+ years in ASIC design with strong CAD tool experience and a track record on large SoCs (>20M
For the Senior SoC Physical Design Lead (Top-Level) position at Apple, Inc., we are reviewing applications now.
The position is based in Beaverton, OR, United States.
This opportunity is part of our work in Engineering.
The advertised compensation is 165..
We aim to respond to suitable candidates as soon as possible.
Position Requirements
10+ Years work experience(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).
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