3D Integration; Physical Implementation engineer

Client Background & Position Overview

Our client is a global leader in information and communication technologies (ICT), with a major R&D facility based in Leuven, Belgium. This European Research Institute (ERI) is at the forefront of innovation, developing cutting‑edge semiconductor technologies to address next‑generation computing needs.

To support multi‑die integration strategies, the team seeks a 3D Integration (Physical Implementation) Engineer with strong experience in backend physical design, clock bus architecture, and 3D integration methodologies.

• Develop and implement high-speed cross-die clocking and interconnect solutions to meet extreme PPA targets.
• Innovate physical design methodologies for advanced integration scenarios (2.5D/3
  
  DIC, Chiplet), including:
  • Cross-die floor planning, interconnect, power delivery, and thermal management.
  • Signoff and verification methodologies tailored for multi-die systems.
  • Reliability analysis techniques specific to 3
    
    DIC technologies.
• Contribute to end-to-end DTCO and STCO flows, collaborating with design, integration, and methodology teams.
• Translate product requirements into scalable physical design strategies and contribute to tool and methodology development.

• Master’s or PhD degree in Electrical Engineering, Computer Science, Physics, or related discipline.
• Deep knowledge of back‑end implementation flows and physical verification (timing, power, IR‑drop, EM).
• Proven experience in physical architecture planning for high‑performance SoCs or 3
  
  DIC‑based designs.
• Familiarity with clock tree synthesis, floor planning, power grid design, and die‑to‑die interfaces.
• Understanding of mainstream semiconductor manufacturing processes.
• 5–10 years of hands‑on experience in physical implementation of complex chips.
• Background in multi‑die or Chiplet‑based systems is a strong plus.
• Strong analytical mindset and communication skills.
• Team player comfortable in a cross‑functional and international environment.

If you are excited by the challenge of shaping the future of 3D integration and physical design in advanced semiconductor technologies, we encourage you to apply. Join a pioneering research environment where your expertise will directly contribute to next‑generation innovation, in a role that offers both technical depth and global impact.